Many audio applications, such as audio analog to digital converters (ADCs) and audio encoder-decoders (CODECs), utilize a serial data port to transmit digitized audio data to other devices in a system. A typical serial data port outputs bits of a serial audio data (SDATA) stream on the selected edges of an associated serial clock (SCLK) signal. In a stereo system, two channels of audio data are time-multiplexed onto the SDATA stream with a left-right clock (LRCK) signal. A master clock (MCLK) signal, which is typically received from an external source, is divided-down to generate internal MCLK signals, which time the operations of the various internal circuits. Advantageously, the utilization of serial ports minimizes the number of pins and associated on-chip driver circuitry.
A typical serial data port can operate in either a master mode or a slave mode. In the master mode, the SCLK and LRCK clock signals are generated internally, in response to the received MCLK signal, and output to the destination of the SDATA stream. In the slave (asynchronous) mode, the SCLK and LRCK clock signals are received from the destination of the SDATA stream.
In an ADC operating in the slave mode, the analog input signal is typically sampled on the rising edge of an internal MCLK signal, which may have an arbitrary phase relationship with the SCLK signal. If the digital data at the SDATA output transitions after the analog data has been sampled at the analog inputs, no noise problems typically result. However, if the digital output data transitions slightly before the analog data has been sampled, then noise can couple into other circuitry on-chip, particularly the analog circuitry, thereby degrading the quality of the output signal. This problem is particularly acute when an ADC is operating in response to an SCLK signal frequency which is close to, or the same as, the frequency of the internal MCLK signal. In this case, every falling edge of SCLK may cause a noisy transition at the SDATA output just prior to analog sampling at the next rising edge of the MCLK signal.
Typical serial audio systems have utilized retiming circuits to delay or otherwise retime SCLK signal such that the digital data transitions at the SDATA output occur after the critical sampling edges of the associated MCLK signal. However, this technique has not performed well, especially when the frequency of the SCLK signal approaches that of the MCLK signal. In particular, as the frequency of the SCLK signal approaches the frequency of the MCLK signal, the timing window within which the SCLK signal can be retimed becomes small. If SCLK signal, and hence the data at the SDATA out, is delayed beyond this timing window, a setup time violation may occur at the destination device, resulting in the reception of incorrect data.
Consequently, new techniques are required for reducing noise at the serial output of and ADC operating in the slave mode. Such techniques should be particularly applicable to ADCs in which the SCLK signal frequency approaches the frequency of the associated MCLK signal.